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Simulink® from The MathWorks® is a powerful graphical modelling system which allows complex systems to be designed using a block diagram methodology.
Xilinx's System Generator for DSP is a blockset for Simulink® which allows the modelling of fixed point systems which can be transformed into VHDL and targeted at an FPGA.
SMT6041 provides additional Simulink® blocksets for VHDL code generation and co-design to support Xilinx's System Generator with Sundance FPGA/DSP/DAQ modules and the following is a list of Blocks supported:
- ComPort Read and ComPort Write
- SDL Read and SDL Write
- SDB Read and SDB Write
- SHB Read and SHB Write
- ADC and DAC for Sundance boards
- Clock Generator
- ZBT RAM
Automatic generation of the bitstreams is supported with the synthesis and implementation tools run from within the Simulink® environment.
SMT6041 users needs to have a hardware design knowledge as System Generator requires detailed parameters; etc.
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