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Lattice Certus NX Space Dev Board

The Adiuvo Space Development board is intended to support the development of demanding space applications, which require low power, high performance and, of course, a low upset rate.




This development board provides the user with a Certus™-NX LFD2NX-40 which is the commercial equivalent of the Certus-NX-RT device offered by CAES.

The Lattice Certus™-NX FPGA provides the user with 40K LUTs, 2.5 Mbit of BRAM, 56 DSP (18×18), 2 ADC and inbuilt 32KHz and 450 MHz Oscillators.

It is also possible to deploy RISC-V processors on this development board using the Lattice Propel tool. Examples of this can be examined in the tutorials below

Propel Builder Hardware Creation

Propel Software Development


Uniquely to this development board is the provision of the RPI Pico, which provides the developer with a wide range of capabilities including:

  1. Clock Generation – Generation of up to 65MHz reference clock using the PIO.
  2. Communications emulation – Emulation of a differential backplane bus
  3. Communications Monitoring – Monitoring and logging communications
  4. Sensor emulation – Emulation of sensors across the system and implementation of failure modes
  5. Complex communications creation – Implementation of a space wire communication protocol between the FPGA and the Pico. This provides a simple interface which can be controlled over the USB communication.
  6. Power management and monitoring – Monitoring the power network, to control, monitor and observe the dissipated power as the FPGA design is used for anger or in under testing for example beam line.



This development board provides an excellent platform for the development of applications including:

  • Deployment Cameras
  • Temperature Control Systems
  • Motor and Actuator Control
  • Telemetry and Telecommand processing
  • Health and Usage Monitoring
  • Radiation Beam Testing for design proving
  • Implementing Compression algorithms
  • Implementing Cryptographic security


  • Certus™-NX LFD2NX-40
  • 80 IO accessible via PMOD
  • 14 ADC Channels – Including ADC Reference
  • 128 Mbit NOR flash for configuration
  • 256 Kbit MRAM memory
  • 100 MHz Oscillator
  • 156.25 MHz Oscillator for the SFP
  • Lattice In-System Programmable Hardware Management Expander
  • RPI Pico

Block Diagram