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Quad Core KeyStone™ DSP + UltraScale™ FPGA Module

SMT6657 Design description



The SMT6657 DSP+FPGA module is a reliable and flexible platform for digital signal processing applications requiring high-performance integer and floating-point computation.
It is applicable to both symmetric multiprocessing applications in which the computational load is shared by the two DSPs and asymmetric applications where one of the DSPs is responsible for hard real-time processing and the other acts as a supervisor, handling all non-deterministic communication and optionally running under control of an operating system.


The SMT6657-KU35 module benefits from the incorporation of three key interface standards, each one the leading standard in its area of the embedded systems field:

1) PCIe/104TM provides tightly integrated high-speed connectivity with PC hosts and also defines a compact and rugged module format.

2) FMC provides an FPGA-oriented data acquisition card interface that is particularly well suited to analogue conversion applications, but also covers image, sensors, robotics and communication interfaces. Due to the flexibility of FPGA I/O, the function of its 68 pins (34-pairs of LVDS interfaces for VITA57.1 LPC-FMC and 8x pairs of 16.3GHz SerDes, as part of VITA 57.1 HPC-FMC) Users can optimised to the needs of the FMC add-on module.

3) Serial RapidIO is a standard designed to address the need for inter-module communication in high bandwidth military and telecoms embedded systems and has become a standard peripheral in all TI’s high-end KeyStone DSPs.


  • PC/104 OneBank™ plug-able module format
  • Two Texas Instrument dual-core TMS320C6657 floating-point DSPs, running @ 1.24 GHz
  • Xilinx Kintex-7 UltraScale KU35 series of FPGA w. 16x GTH transceivers
  • Serial RapidIO and Hyperlink connectivity between DSPs
  • Accepts one VITA57.1 FMC-LPC™ Mezzanine Card data acquisition add-on module
  • Additional stack-down Serial RapidIO connector to SMT-Carrier-GSI
  • Front panel I/O connector carrying gigabit Ethernet and flexible FPGA I/O

Block Diagram