FMCP-ADC3P0 comes as an AC coupled differential (or single-ended, as a build option) ADC module, without any balun on the differential input path to provide maximum accuracy. It supplies four channels of ADC with 3GS/s each at 14bits by using 2 AD9208 ADC ICs (or AD9689BBPZ-2600 for 2.6GS/s) . ADC input is to interface with the JESD204B IP core. The full power bandwidth of this module is 5GHz. Trigger and external clock input connectors are available on the module. The trigger input allows the user to add a timestamp to the sample stream from ADC.
In this module, the ADC input is connected directly to the input differential signal, and the maximum input swing is 1.7V and 2.7V for the differential and single-ended, respectively.
Board clocking structure has been designed based on HMC7044, which provides the possibility of deterministic latency and subclass one synchronization between multiple ADCs.
The module uses 2 ADCs. This device is a JESD204B complaint. They can work at various sample rates, and there is a possibility to enable decimation for the ADC.
Board provides internal VCXO and TCXO clocks. In this case, clocks from HMC7044 go to ADC. This IC also provides the SYSREF clock with known and adjustable delays. According to JESD204B, this also provides REF CLK and SYSREF CLK for FPGA, to achieve the requirement of subclass 1 JESD204B.
The FPGA REF CLK can be used to clock the Rx path. Inside the FPGA transceivers, there are two PLLs. One QPLL – is shared for four transceivers (called quad)- and CPLL one for each transceiver.