Description
The LXD31K2 provides two 16-bit A/D channels with up to 310 Msps data rate and two 16-bit D/A channels with up to 310 Msps data rate with a 1.24 Gsps update rate. All the data interfaces are based on LVCMOS and LVDS signalling. The design is based on the Analog devices AD9652 analogue to digital converters and the Analog devices AD9142A digital to analogue converters.
Analog input and output
Depending on the application requirements it is possible to order the LXD31K2 with either a DC-coupled or an AC coupled analogue front end. The DC-coupled interface is meant for signal acquisitions and playback in the first Nyquist zone while the AC coupled inputs also offer the option for signal acquisition and playback in the second Nyquist zone.
16 bit
Both the ADC and DAC offer 16-bits resolution further contributing to achieve best in class signal to noise ratios.
LVDS signalling
Both the ADC and DAC device make use of LVDS signalling for their data interfaces. This allows easy integration of the LXD31K2 into user FPGA designs without the need to acquire expensive and complex JESD204B interface cores. Thanks to the low pin count implementation the LXD31K2 will work on all Xilinx development boards as well as the Logic-X FPGA FMC carrier boards.
Clock tree
The onboard low noise clock generator ensures easy integration into small single-board systems as well as standalone operation. For larger systems, it is possible to easily synchronize multiple boards by providing an external reference clock. This is a special feature offered by the onboard clock PLL.
Applications
Systems that will benefit greatly from this product are:
- MIMO Applications
- Radar waveform generators and receivers
- Digital Beam Forming
- Medical systems
- Telecommunication systems
- Experimental Physics
- Analogue playback systems
- Aerospace and test instrumentation
- Software defined radio (SDR)
