Description
The LDS NVME HOST IP has been done for beginners and experts in NVMe to drive NVMe PCIe SSD.
The register file interface simplifies the management of the IP for CPU interface or the State Machine interface using AXI bus:
- PCIe RP and EP register configuration is done automatically.
- NVMe register configuration is done automatically.
- Able to manage 8 Name Spaces.
- Able to manage up to 16 IO Queues to fit specific user requirements. Each IO Queue is independent.
- Able to manage 512Bytes or 4096Bytes sector size.
- Able to run nearly all Admin commands in parallel with the IO Queue.
- Many IO command already predefined to ease the use of the IP.
- Configurable IO Queue buffer size to fit user memory requirement in case of small density FPGA: 32KB, 64KB, 128KB or 256KB.
- Able to read all PCIe RP and EP registers.
- Easy connection to embedded Root Port PCIe IP through AXI bus.
The source code format is available for ease of customisation. The customisation can be done by Logic Design Solutions, and DO254 documentation is available on request.
This IP can be customised according to specific needs (application-specific requirements). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specifications.
