Description
Features
- 8 Independent Receivers (Rx)
- 3 Independent Transmitters (Tx) with FIFO
- 68000 microprocessor interface type
- 16-Bit Data-bus
- ARINC 429 Interface: ‘1’ and ‘0’ Lines, RZ code
- Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s
- Multi-Label Capability
- Parity Control: Odd, Even, No Parity, Interrupt Capability
- Independent Interrupt Request Line for Rx and Tx Functions
- Vectored Interrupts
- Direct addressing of all Registers
- FPGA speed grade Operating Frequency dependent
- Available in VHDL source code format for ease of customisation
- Can be customised by Logic Design Solutions
General Description
The M68C429A is an ARINC 429 controller. It is based on TS68C429A but is not strictly compatible with the TS68C429A. it is an enhanced version of the EF4442. The CPU interface is compatible with 16- or 32-bit microprocessor, and the CPU interface can be customised on request.
This macro can be customised according to specific needs (application-specific requirements). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specifications.
