Select Page

Spinosaurus EVO / 2.0MP






SPINOSAURUS EVO is a highly customizable and user-programmable FPGA based on high-speed smart cameras, it is a high-end FPGA camera with a Xilinx Zynq FPGA and high-speed imaging sensor and a 10 Gigabit Ethernet. It includes high-performance ARM System-on-Chip (SoC) technology combined with a turbocharged industrial SONY imaging sensor.

With high-performance FPGA System-on-Chip (SoC) technology, the Spinosaurus EVO camera family opens new dimensions in computer vision. It is a global shutter industrial camera with high frame rates and an open FPGA architecture. With FPGA processing power, the image processing algorithms can run in real time on the camera. Just add your imagination.

Spinosaurus EVO includes a fully customizable and user-programmable open reference design for a high-speed, FPGA-based camera and application development system. Its emphasis is on an open hardware/software development model, high-frame rates, real-time image processing on FPGA and modern graphical user interface support on the PC side. A suite of versatile and high-performance tools for Xilinx Zynq Ultrascale+ SoC FPGA are available to develop algorithms and process data in real time. Images are acquired by SONY PREGIUS GEN3 sensors with a SLVS-EC v1.2 interface (8x 2.3 Gbps), achieving a brilliant image at very high speed. The on-board 4GB LPDDR4 memory with 9.6 GB/s of bandwidth enables usage of complex buffered image processing. The reference design can be easily edited with standard Xilinx Vivado tools. OptoMotive´s custom IP cores seamlessly integrate inside the Xilinx Vivado toolchain. A large portion of FPGA (PL) is free for the programming and development of new algorithms or the implementation of additional IP cores. The 1.2 GHz Dual Core ARM Cortex A53 Programmable Subsystem runs a Linux OS with custom made EVO control and streaming stack (including Zero-copy TCP/IP stack). The SoC also includes dual 600MHz Cortex R5 processors which are free for user data processing. User applications or custom data post-processing can be easily added to any existing design.


  • Laser triangulation – with a readymade Peak detector on-board image processing core;
  • Motion capture – with a ready-made BLOB detector or Running Length Encoder (RLE) on-board image processing core;
  • Industrial process automation – to count, detect, check, verify, read, inspect and test different products, levels, components, etc. at incredible speed;
  • Industrial quality control – to inspect defects, cracks or surface blemishes, size, position, dimension and colour, foreign objects or quality
  • General R&D.



Active pixels H x V 1632 x 1248
Imaging sensor SONY
Resolution (MP) 2.0 MP
Spectral options monochrome
Optical format 9.25 (1/1.7”)
Active pixels (H x V) 4.5 μm
Frame rate (FPS) 470 FPS
Dynamic Range 10bit/12bit 80 dB


ADC Resolution 8/10/12 bit
Analogue Gain 0-48dB at 0.1dB step
Region of Interest YES, with 16 pixel increments
Shutter Type Electronic global shutter
Shutter Time 5 us – 90 s
Pixel Clock Speed 1.9 Gpix/s (16 pixels @ 118.8 MHz)
Exposure Linear, dual gain high dynamic range
Pixel Correction Dead pixel correction and programmable LUT
Trigger Modes Free running, trigger, overlap, pulse width
Trigger Features Delay 0 – 1000 ms, LP Filter 1.5Hz – 100 kHz
Shutter Resolution 1.56 us
FPGA Xilinx Zynq Ultrascale+ ZU4CG
Free FPGA % Up to 50%, most of 728 slices of DSP are free.
Volatile Memory 2 GB LPDDR4 with 9.6 GB/s bandwidth
Non-volatile Memory 64 MB QSPI flash, 16 GB eMMC
Lens Mount C-mount (1” 32G thread)
Temp Range 0 – 50°C
Mass TBD
Protection Up to IP67 with housing
Housing Material CNC-machined aluminum, anodized
RoHS RoHS compliant
Fixing Holes 4x M3 OEM / 5 x M6 on housing
Input Voltage DC 9-36V or 5V (OEM)
Consumption up to 30W
IO Isolation 3x IN / 3x OUT opto-isolated
Connectors 10G SFP+, 10 pin Hirose HR10A, ZIF or OEM
On-board Image Processing As an option (if an IP Core is integrated)
Open Reference Design Yes
Open architecture Yes
Software Compatible with OptoMotive EVO software (full source included)
Operating System Windows 7, Windows 10, 64bit or 32bit
Development Tools Xilinx Vivado/SDK version 2018.2 or later.; Microsoft Visual Studio 2017